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n2206 / 32902rm(ot)no.7141-1/54 ? ccb is a trademark of sanyo electric co., ltd. ? ccb is sanyo?s original bus format and all the bus addresses are controlled by sanyo. any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein. LC75810E lc75810t overview the LC75810E and lc75810t are 1/8 to 1/10 duty dot matrix lcd display controllers/drivers that support the display of characters, numbers, and symbols. in addition to generating dot matrix lcd drive signals based on data transferred serially from a microcontroller, the LC75810E and lc75810t also provide on-chip character display rom and ram to allow display systems to be implemented easily. features ? controls and drives a 5 7, 5 8, or 5 9 dot matrix lcd. ? supports accessory display segment drive (up to 80 segments) ? display technique: 1/8-duty, 1/4-bias drive (5 7 dots, 6 7 dots) 1/9-duty, 1/4-bias drive (5 8 dots, 6 8 dots) 1/10-duty, 1/4-bias drive (5 9 dots, 6 9 dots) ? display digits: 16 digits 1 line (5 7 dots), 15 digits 1 line (5 8 or 5 9 dots) 13 digits 1 line (6 7, 6 8, or 6 9 dots) ? display control memory cgrom: 240 characters (5 7, 5 8, or 5 9 dots) cgram: 16 characters (5 7, 5 8, or 5 9 dots) dcram: 64 8 bits alatch: 80 bits ? instruction function display on/off control smooth up, down, left, and right scrolling of the display ? provides a backup function based on power saving mode ? the frame frequency of the common and segment output waveforms can be controlled by instructions. ? built-in display contrast adjustment circuit ? serial data input suppor ts ccb format communication with the system controller ? independent lcd driver block power supply v lcd ? provides a res pin for ic internal initialization. ? rc oscillator circuit cmos ic 1/8 to 1/10 duty dot matrix lcd display controllers/drivers orderin g numbe r : enn*7141
LC75810E/t no.7141-2/54 package dimensions unit: mm 3151a-qfp100e [LC75810E] 20.0 23.2 14.0 17.2 0.15 0.8 (2.7) 3.0max 0 .1 0.3 0.65 (0.58) 13 0 80 51 31 50 100 81 sanyo: qfp100e unit: mm 3274-tqfp100 [lc75810t] 100 12 5 26 50 51 75 76 14.0 (1.0) (1.0) 0 .1 0.12 5 16.0 0.2 0.5 1.2max 0.5 14.0 16.0 sanyo: tqfp100
LC75810E/t no.7141-3/54 pin assignments (top view) com10/s79 com6 com5 vdd vlcd1 s4 s10 s16 s21 s15 s34 s39 s44 s59 s58 s49 s50 s51 s52 s53 s54 s55 s56 s57 s60 s61 s62 s63 s64 s65 s66 s67 s68 s69 s70 s71 s72 s73 s74 s75 s76 s77 s78 s3 s9 s2 s1 di cl com9/s80 LC75810E (qfp100e) com8 com7 com4 com3 com1 com2 vlcd vlcd0 vlcd2 vlcd3 osc vss res s33 s32 s31 s30 s29 ce 51 80 50 81 31 100 30 1 s8 s7 s6 s5 s14 s20 s13 s12 s11 s19 s18 s17 s25 s24 s23 s22 s28 s27 s26 s38 s37 s36 s35 s43 s42 s41 s40 s48 s47 s46 s45 s55 s51 s52 s53 s54 s56 s57 s58 s59 s60 s61 s62 s63 s64 s65 s66 s67 s68 s69 s70 s71 s72 s73 s74 s75 s5 s11 s4 s3 s2 s1 s77 com10/s79 s78 com9/s80 s76 lc75810t (tqfp100) com8 com7 com6 com4 com5 com2 com3 com1 vlcd vdd vlcd1 vlcd0 vlcd2 vss vlcd3 osc ce res cl s35 s34 s33 s32 s31 s29 s30 s27 s28 s26 di 51 75 50 76 26 100 25 1 s10 s9 s8 s7 s6 s16 s22 s15 s14 s13 s12 s21 s20 s19 s18 s17 s25 s24 s23 s40 s39 s38 s37 s36 s45 s44 s43 s42 s41 s50 s49 s48 s47 s46
LC75810E/t no.7141-4/54 specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol conditions ratings unit v dd max v dd ? + ? + ? + ? + ? + ? + ? + = ? + ? + allowable operating ranges at ta = ? 40 c to + 85 c, v ss = 0v ratings parameter symbol conditions min. typ. max. unit v dd v dd 2.7 6.0 when the display contrast adjustm ent circuit is used. 7.0 10.0 supply voltage v lcd when the display contrast adjustm ent circuit is not used. 4.5 10.0 v output voltage v lcd 0 v lcd 0 4.5 v lcd v v lcd 1 v lcd 1 3/4 v lcd 0 v lcd 0 v lcd 2 v lcd 2 2/4 v lcd 0 v lcd 0 input voltage v lcd 3 v lcd 3 1/4 v lcd 0 v lcd 0 v input high level voltage v ih ce, cl, di, res 0.8 v dd 6.0 v input low level voltage v il ce, cl, di, res 0 0.2 v dd v recommended external resistance r osc osc 10 k ?
LC75810E/t no.7141-5/54 electrical characteristics for the allowable operating ranges ratings parameter symbol conditions min. typ. max. unit hysteresis v h ce, cl, di, res 0.1v dd v input high level current i ih ce, cl, di, res : v i = = ? = ? ? = ? ? = = = ? + = ? + ? = ? + = ? = = = = = = = ? excluding these resistors to the common and segment drivers figure 1 v ss contrast adjuster v lcd 2 v lcd 1 v lcd 0 v lcd v lcd 3
LC75810E/t no.7141-6/54 ? when cl is stopped at the low level t l t h vil vil vih 50% vih t ds vil vih t ch t cs t cp t dh ce cl di ? when cl is stopped at the high level t h t l vil vih 50% t ds vil vil vih vih t ch t cs t cp figure 2 t dh ce cl di block diagram s80/com9 scroll counter cgram 5 9 16 b its clock generator timing generator address register instruction register common driver instruction decoder address counter dcram 64 8 b its cgrom 5 9 240 b its shift register ccb interface latch segment driver osc di ce cl s1 s78 com1 s79/com10 res v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 com8 contrast adjuster v lcd v dd alatch 80bits
LC75810E/t no.7141-7/54 pin functions pin no. pin LC75810E lc75810t function active level i/o handling when unused s1 to s78 s79/com10 s80/com9 3 to 80 81 82 1 to 78 79 80 segment driver outputs the s79/com10 and s80/com9 pins can be used as common driver outputs under the ?set di splay technique? instruction. ? o open com1 to com8 90 to 83 88 to 81 common driver outputs ? o open osc 98 96 oscillator connection. an oscillato r circuit is formed by connecting an external resistor and c apacitor at this pin. ? i/o vdd ce 100 98 h i cl 1 99 i di 2 100 serial data transfer inputs. t hese pins are c onnected to the microcontroller. ce: chip enable cl: synchronization clock di: transfer data ? i gnd res 99 97 reset signal input ? when res is low (v ss ) ? display off s1 to s78 = ?l? (v ss ) s79/com10 and s80/com9 = ?l? (v ss ) com1 to com8 = ?l? (v ss ) ? serial data transfer is disabled. ? the osc pin oscillator is stopped. ? when res is high (v dd ) ? display on after a ?display on/ off control? (display on state setting) instruction is executed. ? serial data transfers are enabled. ? the osc pin oscillator operates. l i gnd v lcd 0 93 91 lcd drive 4/4 bias voltage (high level) supply pin. the level on this pin can be changed by the disp lay contrast adjustment circuit. however, v lcd 0 must be greater than or equal to 4.5 v. also, external power must not be applied to this pin since the pin circuit includes the display cont rast adjustment circuit. ? o open v lcd 1 94 92 lcd drive 3/4 bias voltage (middle level) supply pin. this pin can be used to supply the 3/4 v lcd 0 voltage level externally. ? i open v lcd 2 95 93 lcd drive 2/4 bias voltage (middle level) supply pin. this pin can be used to supply the 2/4 v lcd 0 voltage level externally. ? i open v lcd 3 96 94 lcd drive 1/4 bias voltage (middle level) supply pin. this pin can be used to supply the 1/4 v lcd 0 voltage level externally. ? i open v dd 91 89 logic block power supply connec tion. provide a voltage of between 2.7 and 6.0 v. ? ? ? v lcd 92 90 lcd driver block power supply connection. provide a voltage of between 7.0 and 10.0 v when the di splay contrast adjustment circuit is used and provide a voltage of between 4.5 and 10.0 v when the circuit is not used. ? ? ? v ss 97 95 power supply connec tion. connect to ground. ? ? ?
LC75810E/t no.7141-8/54 block functions ? ac (address counter) ac is a counter that provides the dcram address. the address is automatically modified internally, and the lcd display state is retained. ? dcram (data control ram) dcram is the ram that is used to store display data expr essed as 8-bit character codes. (these character codes are converted to 5 7, 5 8, or 5 9 dot matrix character patterns using cgrom or cgram.) dcram has a capacity of 64 8 bits, and can hold 64 characters. the table below lists the correspondence between the 6-bit dcram address loaded into ac and the display position on the lcd panel. ? for a 64 digits 1 line display structure (for a ?set display technique? instruction with 0z1 = 0 and 0z2 = 0) when the dcram address lo aded into ac is 00h display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 61 62 63 64 dcram address (hexadecimal) first line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 3c 3d 3e 3f however, when the display smooth scrolling is performed, the dcram address shifts as follows. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 61 62 63 64 dcram address (hexadecimal) first line 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 3d 3e 3f 00 shift to the left by 1 character digit display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 61 62 63 64 dcram address (hexadecimal) first line 3f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 3b 3c 3d 3e shift to the right by 1 character digit note that the display area on the lcd is display digits 1 to 16 on the first line when a display technique is 5 7, 5 8, or 5 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 7, 6 8, or 6 9 dots. ? for a 32 digits 2 lines display structure (for a ?set display technique? instruction with 0z1 = 1 and 0z2 = 0) when the dcram address lo aded into ac is 00h display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 29 30 31 32 first line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 1c 1d 1e 1f dcram address (hexadecimal) second line 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 3c 3d 3e 3f however, when the display smooth scrolling is performed, the dcram address shifts as follows. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 29 30 31 32 first line 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 1d 1e 1f 00 dcram address (hexadecimal) second line 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 3d 3e 3f 20 shift to the left by 1 character digit display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 29 30 31 32 first line 1f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 1b 1c 1d 1e dcram address (hexadecimal) second line 3f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 3b 3c 3d 3e shift to the right by 1 character digit display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 29 30 31 32 first line 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 3c 3d 3e 3f dcram address (hexadecimal) second line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 1c 1d 1e 1f shift to the up or down by 1 character digit note that the display area on the lcd is display digits 1 to 16 on the first line when a display technique is 5 7, 5 8, or 5 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 7, 6 8, or 6 9 dots.
LC75810E/t no.7141-9/54 ? for a 16 digits 4 lines display structure (for a ?set display technique? instruction with 0z1 = 0 and 0z2 = 1) when the dcram address lo aded into ac is 00h display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 first line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f second line 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f third line 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f dcram address (hexadecimal) fourth line 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f however, when the display smooth scrolling is performed, the dcram address shifts as follows. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 first line 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 second line 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 10 third line 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 20 dcram address (hexadecimal) fourth line 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 30 shift to the left by 1 character digit display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 first line 0f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e second line 1f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e third line 2f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e dcram address (hexadecimal) fourth line 3f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e shift to the right by 1 character digit display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 first line 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f second line 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f third line 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f dcram address (hexadecimal) fourth line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f shift to the up by 1 character digit display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 first line 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f second line 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f third line 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f dcram address (hexadecimal) fourth line 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f shift to the down by 1 character digit note that the display area on the lcd is display digits 1 to 16 on the first line when a display technique is 5 7, 5 8, or 5 9 dots, and it is display digits 1 to 13 on the first line when a display technique is 6 7, 6 8, or 6 9 dots. note ? 2: the dcram address is expressed in hexadecimal. lsb msb dcram address da0 da1 da2 da3 da4 da5 example: when the dcram address is 2eh da0 da1 da2 da3 da4 da5 0 1 1 1 0 1 note ? 3: 5 7 dots ? ? ? 16-digit display 5 7 dots. 5 8 dots ? ? ? 16-digit display 4 8 dots. 5 9 dots ? ? ? 16-digit display 3 9 dots. 6 7 dots ? ? ? 13-digit display 6 7 dots. 6 8 dots ? ? ? 13-digit display 6 8 dots. 6 9 dots ? ? ? 13-digit display 6 9 dots. least significant bit most significant bit hexadecimal hexadecimal
LC75810E/t no.7141-10/54 ? cgrom (character generator rom) cgrom is the rom that is used to generate the 240 kinds of 5 7, 5 8, or 5 9 dot matrix character patterns from the 8-bit character codes. cgrom has a capacity of 240 45 bits. when a character code is written to dcram, the character pattern stored in the cgrom corresponding to th e character code is displayed at the position on the lcd corresponding to the dcram address loaded into ac. ? cgram (character generator ram) cgram is the ram to which user progr ams can freely write arb itrary character patterns. up to 16 kinds of 5 7, 5 8, or 5 9 dot matrix character patterns can be stored. cgram has a capacity of 16 45 bits. ? alatch (additional data latch) alatch is the latch that is used to store the adata disp lay data for the accessory display. alatch has a capacity of 80 bits, and the stored display data is displayed directly without the use of cgrom or cgram. ? sc (scroll counter) sc is the counter that is used to scroll the display in the left, right, up, or down directions in dot units. since this function scrolls in dot units, it implements smooth scrolling. reset function the LC75810E and lc75810t are reset when a low level is applied to the res pin at power on and, in normal mode. on a reset the LC75810E and lc75810t create a display with all lcd pa nels turned off. however, after a reset applications must set the contents of dcram, alatch, and cgram before turning on display with a ?display on/off control? instruction since the contents of these memories are undefined. that is, applications must execute the following instructions. ? set display technique ? dcram data write ? alatch data write (if alatch is used.) ? cgram data write (if cgram is used.) ? set ac and sc addresses ? set display contrast (if the display c ontrast adjustment circuit is used.) after executing the above instructions, applications must turn on the display with a ?display on/off control? instruction. note that when applications turn off in the normal mode, applications must turn off the display with a ?display on/off control? instruction. (see the detailed instruction descriptions.) serial data transfer format ? when cl is stopped at the low level instruction data up to 144 bits ccb address 8 bits a3a2a1a0 b3b2 d 14 3 d 14 2 d4d3d2 10 00 111 0d 0 d 1 b1 ce di cl b0 ? when cl is stopped at the high level instruction data up to 144 bits ccb address 8 bits a3a2a1a0 b3b2 d 14 3 d 14 2 d4d3d2 000 11 110 d0 d1 b1 ce di cl b0 ? ccb address: 4eh ? d0 to d143: instruction data the data is acquired on the rising edge of the cl signal and latched on the falling edge of the ce signal. when transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next in struction data transfer is significantly longer than the instru ction execution time.
LC75810E/t no.7141-11/54 execution time ( ? 4) 0 s 0 s/27 s ( ? 5) 27 s/162 s ( ? 6) 27 s 27 s/ti s ( ? 8) 0 s 27 s/40.5 s ( ? 10) 0 s d143 1 0 1 0 1 0 1 0 d142 0 1 1 0 0 1 1 0 d141 0 0 0 1 1 1 1 0 d140 0 0 0 0 0 0 0 1 d139 0 bu 0 0 0 0 0 0 d138 fc sc x x x x x x d137 dt2 a d/u x im2 x x x d136 dt1 m r/l x im1 x wm ctc d135 x dg16 x x x ad80 ca7 x d134 x dg15 x x x ad79 ca6 x d133 x dg14 x da5 da5 ad78 ca5 x d132 x dg13 x da4 da4 ad77 ca4 x d131 x dg12 vs3 da3 da3 ad76 ca3 ct3 d130 dw dg11 vs2 da2 da2 ad75 ca2 ct2 d129 oz2 dg10 vs1 da1 da1 ad74 ca1 ct1 d128 oz1 dg9 vs0 da0 da0 ad73 ca0 ct0 d127 dg8 x x ac7 ad72 x d126 dg7 x x ac6 ad71 x d125 dg6 x x ac5 ad70 x d124 dg5 x x ac4 ad69 cd45 d123 dg4 x va3 ac3 ad68 cd44 d122 dg3 hs2 va2 ac2 ad67 cd43 d121 dg2 hs1 va1 ac1 ad66 cd42 d120 dg1 hs0 va0 ac0 ad65 cd41 d119 x ad64 cd40 d118 x ad63 cd39 d117 x ad62 cd38 d116 x ad61 cd37 d115 x ad60 cd36 d114 ha2 ad59 cd35 d113 ha1 ad58 cd34 d112 ha0 ad57 cd33 d111 ad56 cd32 ? ? ? ? ? ? ? ? ? d81 a d2 6 cd2 d80 a d2 5 cd1 d79 a d24 ? ? ? ? ? ? d5 7 a d 2 d5 6 a d1 d5 5 ? ? ? d1 d0 instruction set display technique display on/off control display scroll set ac and sc addresses dcram data write ( ? 7) alatch data write cgram data write ( ? 9) set display contrast x: don?t care notes ? 4: the execution times listed here apply when fosc = 300 khz. the execution times differ when the oscillator frequency fosc differs. example: when fosc = 210 khz 27 s = 39 s 162 s = 232 s ti s = ti 1.43 s 40.5 s = 58 s ? 5: note that when the power saving mode (bu = 1) is set, the execution time is 27 s (when fosc = 300 khz). ? 6: the execution time must be seen as being 162 s (when fosc = 300 khz) if another ?display scroll? instruction is executed immediately after a preceding ?display scroll? instruction. ? 7, ? 8: note that the data format differs when a ?dcram data write? instruction is executed in normal increment mode (im1 = 1, im2 = 0) or super-increment mode (im1 = 0, im2 = 1). also note that the execution time is ti s (when fosc = 300 khz) if a ?dcram data write? instruction is executed in super-increment mode. (see detailed instruction descriptions.) ? 9, ? 10: note that the data format differs when a ?cgram data write? instruction is executed in double write mode (wm = 1). also note that the execution time is 40.5 s (when fosc = 300 khz) if a ?cgram data write? instruction is executed in double write mode. (see detailed instruction descriptions.) 300 210 300 210 300 210 300 210 instruction table
LC75810E/t no.7141-12/54 detailed instruction descriptions ? set display technique ? ? ? code d128 d129 d130 d131 d132 d 133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 oz1 oz2 dw x x x x x dt1 dt2 fc 0 0 0 0 1 x:don?t care dt1, dt2: set the display technique output pins dt1 dt2 display technique s80/com9 s79/com10 0 0 1/8 duty, 1/4 bias drive s80 s79 1 0 1/9 duty, 1/4 bias drive com9 s79 0 1 1/10 duty, 1/4 bias drive com9 com10 ? 11: sn (n = 79, 80): segment output comn (n = 9, 10): common output fc: set the frame frequency of the common and segment output waveforms frame frequency fc 1/8 duty, 1/4 bias drive f8[hz] 1/9 duty, 1/4 bias drive f9[hz] 1/10 duty, 1/4 bias drive f10[hz] 0 fosc 3072 fosc 3456 fosc 3840 1 fosc 1536 fosc 1728 fosc 1920 oz1, oz2: set the display structure oz1 oz2 display structure 0 0 64 digits 1 line display structure 1 0 32 digits 2 lines display structure 0 1 16 digits 4 lines display structure ? 12: see block functions (dcram) dw: set the dot font width dw dot font width number of display digits 0 5-dot font width 16 digits 1 line (5 7 dots), 15 digits 1 line (5 8 or 5 9 dots) 1 6-dot font width 13 digits 1 line (6 7, 6 8, or 6 9 dots) ? 13: ? 5-dot font width (5 7, 5 8, or 5 9 dots) com2 com3 com4 com5 com6 com7 com8 s80/com9 s79/com10 com1 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s71 s72 s73 s74 s75 s76 s77 s78 com10/s79 com9/s80 ? 6-dot font width (6 7, 6 8, or 6 9 dots) com2 com3 com4 com5 com6 com7 com8 s80/com9 s79/com10 com1 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s67 s68 s69 s70 s71 s72 s73 s74 s75 s76 s77 s78
LC75810E/t no.7141-13/54 ? display on/off control ? ? ? code d120 d121 d122 d123 d124 d125 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 dg1 dg2 dg3 dg4 dg5 dg6 dg7 dg8 dg9 dg1 0 dg1 1 dg1 2 dg1 3 dg1 4 dg1 5 dg1 6 m a sc bu 0 0 1 0 m, a: specifies the data to be turned on or off. m a display operating state 0 0 both mdata and adata are turned off. (the display is fo rcibly turned off, regardless of the dg1 to dg16 data.) 0 1 only adata is turned on. (the ad ata of display digits specified by the dg1 to dg16 data are turned on.) 1 0 only mdata is turned on. (the md ata of display digits specified by the dg1 to dg16 data are turned on.) 1 1 both mdata and adata are turned on. (the mdata and adata of display digits specif ied by the dg1 to dg16 data are turned on. ) *14: mdata, adata 5 7 dot matrix 5 8 dot matrix 5 9 dot matrix ? ? ? ? ? adata ? ? ? mdata ? ? ? ? ? adata ? ? ? mdata ? ? ? ? ? adata ? ? ? mdata 6 7 dot matrix 6 8 dot matrix 6 9 dot matrix ? ? ? ? ? adata ? ? ? mdata ? ? ? ? ? adata ? ? ? mdata ? ? ? ? ? adata ? ? ? mdata dg1 to dg16: specifies the display digit. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 display digit data dg1 dg2 dg3 dg4 dg5 dg6 dg7 dg8 dg9 dg10 dg11 dg12 dg13 dg14 dg15 dg16 for example, if dg1 to dg8 are 1, and dg9 to dg16 are 0, then display digits 1 to 8 will be turned on, and display digits 9 to 16 will be turned off (blanked). sc: controls the common and segment output pins. sc common and segment output pin states 0 output of lcd drive waveforms 1 fixed at the v ss level (all segments off) note ? 15: when sc is 1, the s1 to s80 and com1 to com10 output pins are set to the v ss level, regardless of the m, a, and dg1 to dg16 data. bu: controls the normal mode and power saving mode. bu mode 0 normal mode 1 power saving mode (in this mode, the osc pin osc illator is stopped, and the common and s egment pins are set to the v ss level. in this mode, instructions other than the ?display on/off control? and ?s et display contrast? instructi ons cannot be exec uted. thus applic ations must set the ic to n ormal mode before executing any of the other instructions.)
LC75810E/t no.7141-14/54 ? display scroll ? ? ? code d120 d121 d122 d123 d124 d125 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 hs0 hs1 hs2 x x x x x vs0 vs1 vs2 vs3 x x x x r/l d/u x 0 0 0 1 1 x: don?t care hs0 to hs2: set the amount of smooth scrolling to be applied to mdata in the left/right direction. hs0 hs1 hs2 amount of smooth scrolling to be applied to mdata in the left/right direction 0 0 0 no shift in either the left or right direction 1 0 0 shift 1 dot to the left or righ t. (the shift direction (left or right ) is specified wi th the r/l data.) 0 1 0 shift 2 dots to the left or right. (the shift direction (left or right ) is specified wi th the r/l data.) 1 1 0 shift 3 dots to the left or right. (the shift direction (left or right ) is specified wi th the r/l data.) 0 0 1 shift 4 dots to the left or right. (the shift direction (left or right ) is specified wi th the r/l data.) 1 0 1 shift 5 dots to the left or right. (the shift direction (left or right ) is specified wi th the r/l data.) 0 1 1 shift 6 dots to the left or right. (the shift direction (left or right ) is specified wi th the r/l data.) vs0 to vs3: set the amount of smooth scrolling to be applied to mdata in the up/down direction. vs0 vs1 vs2 vs3 amount of smooth scrolling to be applied to mdata in the up/down direction 0 0 0 0 no shift in either the up or down direction 1 0 0 0 shift 1 dot to the up or down. (the shift dire ction (up or down) is spec ified with the d/u data.) 0 1 0 0 shift 2 dots to the up or down. (the shift direction (up or down) is spec ified with the d/u data.) 1 1 0 0 shift 3 dots to the up or down. (the shift direction (up or down) is spec ified with the d/u data.) 0 0 1 0 shift 4 dots to the up or down. (the shift direction (up or down) is spec ified with the d/u data.) 1 0 1 0 shift 5 dots to the up or down. (the shift direction (up or down) is spec ified with the d/u data.) 0 1 1 0 shift 6 dots to the up or down. (the shift direction (up or down) is spec ified with the d/u data.) 1 1 1 0 shift 7 dots to the up or down. (the shift direction (up or down) is spec ified with the d/u data.) 0 0 0 1 shift 8 dots to the up or down. (the shift direction (up or down) is spec ified with the d/u data.) 1 0 0 1 shift 9 dots to the up or down. (the shift direct ion (up or down) is specif ied with the d/u data.) ( ? 16) 0 1 0 1 shift 10 dots to the up or down. (the shift direct ion (up or down) is specif ied with the d/u data.) ( ? 17) notes: ? 16: this shift cannot be used when mdata is 5 7 or 6 7 dots. ? 17: this shift cannot be used when mdata is 5 7, 5 8, 6 7 or 6 8 dots. r/l: specifies the mdata shift direction (left or right). d/u: specifies the mdata shift direction (up or down). r/l mdata shift direction (left or right) d/u mdata shift direction (up or down) 0 shift left 0 shift up 1 shift right 1 shift down ? 18 example of the ?display scroll? instruction execution assume that a 32 digits 2 lines display structure (oz1 = 1, oz2 = 0) has been set up with the ?set display technique? instruction, and that the following data has been writte n to dcram with the ?dcram data write? instruction. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 first line a b c d e f g h i j k l m n o p q r s t u v w x y z < > zyxw dcram data second line 0 1 2 3 4 5 6 7 8 9 a b c d e f g h i j k l m n o p q r s t u v
LC75810E/t no.7141-15/54 ? display state (1) with no shifting in any direction, left, right, up, or down. hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/u 0 0 0 0 0 0 0 x x x: don?t care (5 7 dot matrix) (6 7 dot matrix) ? display state (2) shifted 3 dots to the left relative to display state (1) hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/u 1 1 0 0 0 0 0 0 0 (5 7 dot matrix) (6 7 dot matrix) ? display state (3) shifted 6 dots to the left relative to display state (1) shifted 3 dots to the left relative to display state (2) hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/ u hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/u 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 (5 7 dot matrix) (6 7 dot matrix)
LC75810E/t no.7141-16/54 ? display state (4) shifted 4 dots to the up relative to display state (1) hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/u 0 0 0 0 0 1 0 0 0 (5 7 dot matrix) (6 7 dot matrix) ? display state (5) shifted 8 dots to the up relative to display state (1) shifted 4 dots to the up relative to display state (4) hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/ u hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/u 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 (5 7 dot matrix) (6 7 dot matrix) ? display state (6) shifted 3 dots to the left and 4 dots to the up relative to display state (1) hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/u 1 1 0 0 0 1 0 0 0 (5 7 dot matrix) (6 7 dot matrix)
LC75810E/t no.7141-17/54 ? display state (7) shifted 6 dots to the left and 8 dots to the up relative shifted 8 dots to the up relative to display state (3) to display state (1) hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/ u hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/u 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 shifted 6 dots to the left relative to display state (5) shifted 3 dots to the left and 4 dots to the up relative to display state (6) hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/ u hs0 hs1 hs2 vs0 vs1 vs2 vs3 r/l d/u 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 (5 7 dot matrix) (6 7 dot matrix) ? set ac and sc addresses ? ? ? code d112 d113 d114 d115 d116 d 117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 ha0 ha1 ha2 x x x x x va0 va1 va2 va3 x x x x code d128 d129 d130 d131 d132 d 133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 da0 da1 da2 da3 da4 da5 x x x x x 0 0 1 0 0 x: don?t care da0 to da5: dcram address da0 da1 da2 da3 da4 da5 lsb msb least most significant bit significant bit ha0 to ha2: dot address in the horizontal direction for the dot matrix character pattern ha0 ha1 ha2 lsb msb least most significant bit significant bit va0 to va3: dot address in the vertical direction for the dot matrix character pattern va0 va1 va2 va3 lsb msb least most significant bit significant bit
LC75810E/t no.7141-18/54 ? 19 the figure below lists the correspondence between the data ha0 to ha2 which is dot address in the horizontal direction and the dot matrix character pattern, and the correspondence between the data va0 to va3 which is dot address in the vertical direction a nd the dot matrix character pattern. ? 5-dot font width: 5 7, 5 8, or 5 9 dots va0 to va3 (hex) 0 1 2 3 4 5 6 7 8 9 dot address in the vertical direction ? the area at ha0 to 2 = 5h is allocated to the space at the right of the dot matrix character pattern. ? the area at va0 to 3 = 7h, for 5 7 dot characters, is allocated to the space at the bottom of the dot matrix character pattern. ? the area at va0 to 3 = 8h is illegal for 5 7 dot characters. for 5 8 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. ? the area at va0 to 3 = 9h is illegal for 5 7 or 5 8 dot characters. for 5 9 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. dot address in the horizontal direction ha0 to ha2 (hex) 0 1 2 3 4 5 ? 6-dot font width: 6 7, 6 8, or 6 9 dots ? the area at ha0 to 2 = 5h is allocated to the space at the right of the dot matrix character pattern. ? the area at va0 to 3 = 7h, for 6 7 dot characters, is allocated to the space at the bottom of the dot matrix character pattern. ? the area at va0 to 3 = 8h is illegal for 6 7 dot characters. for 6 8 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. ? the area at va0 to 3 = 9h is illegal for 6 7 or 6 8 dot characters. for 6 9 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. 0 1 2 3 4 5 dot address in the horizontal direction ha0 to ha2 (hex) va0 to va3 (hex) 0 1 2 3 4 5 6 7 8 9 dot address in the vertical direction ? 20: example of the ?set ac and sc addresses? instruction execution assume that a 32 digits 2 lines display structure (oz1 = 1, oz2 = 0) has been set up with the ?set display technique? instruction, and that the following data has been writte n to dcram with the ?dcram data write? instruction. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 first line (dcram address (hexadecimal)) a (00) b (01) c (02) d (03) e (04) f (05) g (06) h (07) i (08) j (09) k (0a) l (0b) m (0c) n (0d) o (0e) p (0f) dcram data second line (dcram address (hexadecimal)) 0 (20) 1 (21) 2 (22) 3 (23) 4 (24) 5 (25) 6 (26) 7 (27) 8 (28) 9 (29) a (2a) b (2b) c (2c) d (2d) e (2e) f (2f) display digit 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 first line (dcram address (hexadecimal)) q (10) r (11) s (12) t (13) u (14) v (15) w (16) x (17) y (18) z (19) < (1a) > (1b) z (1c) y (1d) x (1e) w (1f) dcram data second line (dcram address (hexadecimal)) g (30) h (31) i (32) j (33) k (34) l (35) m (36) n (37) o (38) p (39) q (3a) r (3b) s (3c) t (3d) u (3e) v (3f)
LC75810E/t no.7141-19/54 ? when da0 to 5 is set to 07h, ha0 to 2 is set to 0h, and va0 to 3 is set to 0h. ha0 ha1 ha2 va0 va1 va2 va3 da0 da1 da2 da3 da4 da5 0 0 0 0 0 0 0 1 1 1 0 0 0 (5 7 dot matrix) (6 7 dot matrix) ? when da0 to 5 is set to 09h, ha0 to 2 is set to 4h, and va0 to 3 is set to 0h. ha0 ha1 ha2 va0 va1 va2 va3 da0 da1 da2 da3 da4 da5 0 0 1 0 0 0 0 1 0 0 1 0 0 (5 7 dot matrix) (6 7 dot matrix) ? when da0 to 5 is set to 0fh, ha0 to 2 is set to 0h, and va0 to 3 is set to 3h. ha0 ha1 ha2 va0 va1 va2 va3 da0 da1 da2 da3 da4 da5 0 0 0 1 1 0 0 1 1 1 1 0 0 (5 7 dot matrix) (6 7 dot matrix)
LC75810E/t no.7141-20/54 ? when da0 to 5 is set to 14h, ha0 to 2 is set to 1h, and va0 to 3 is set to 2h. ha0 ha1 ha2 va0 va1 va2 va3 da0 da1 da2 da3 da4 da5 1 0 0 0 1 0 0 0 0 1 0 1 0 (5 7 dot matrix) (6 7 dot matrix) ? when da0 to 5 is set to 34h, ha0 to 2 is set to 3h, and va0 to 3 is set to 6h. ha0 ha1 ha2 va0 va1 va2 va3 da0 da1 da2 da3 da4 da5 1 1 0 0 1 1 0 0 0 1 0 1 1 (5 7 dot matrix) (6 7 dot matrix) ? dcram data write ? ? ? code d120 d121 d122 d123 d124 d125 d126 d127 d128 d129 d130 d131 d 132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 da0 da1 da2 da3 da4 da5 x x im1 im2 x 0 0 1 0 1 x: don?t care da0 to da5: dcram address da0 da1 da2 da3 da4 da5 lsb msb least significant bit most significant bit ac0 to ac7: dcram data (character code) ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 lsb msb least significant bit most significant bit this instruction writes the 8 bits of data ac0 to ac7 to dcram. this data is a character code, and is converted to a 5 7, 5 8, or 5 9 dot matrix display data using cgrom or cgram.
LC75810E/t no.7141-21/54 im1 and im2: sets the met hod of writing data to dcram im1 im2 dcram data write method 0 0 normal dcram data write (specifies the dcram address and writes the dcram data.) 1 0 normal increment mode dcram data write (increments the dcram address by + 1 each time data is written to dcram.) 0 1 super-increment mode dcram data write (writes 2 to 16 characters of dcram data in a single operation.) ? 21 ? dcram data write method when im1 is 0 and im2 is 0. dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) (1) (1) (1) 24 bits 24 bits 24 bits 24 bits (1) ce di dcram ccb address ccb address ccb address ccb address ? dcram data write method when im1 is 1 and im2 is 0. (instructions other than the ?dcram data write? instruction cannot be executed.) dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) (4) (3) (3) (3) (3) 8 bits 8 bits 8 bits 24 bits (2) di dcram ce (instructions other than the ?dcram data write? instruction cannot be executed.) ccb address ccb address ccb address ccb address ccb address ccb address 8 bits 16 bits ? dcram data write method when im1 is 0 and im2 is 1. dcram data write finishes dcram data write finishes dcram data write finishes instruction execution time (ti s) instruction execution time (ti s) instruction execution time (ti s) (5) (5) n bit n bit (5) ce di dcram n bit ccb address ccb address ccb address ti = 13.5 s ( -1) (n = 8m + 16, m is an integer between 2 and 16 th at is the number of characters written as dcram data.) for example when n = 32 bits (m = 2): ti = 40.5 s (when fosc = 300 khz) when n = 80 bits (m = 8): ti = 121.5 s (when fosc = 300 khz) when n = 144 bits (m = 16): ti = 229.5 s (when fosc = 300 khz) note that the instruction execution time of 27 s and ti values in s apply when fosc = 300 khz, and that these times will differ when the oscillator frequency fosc differs. n 8
LC75810E/t no.7141-22/54 data format (1) (24 bits) code d120 d121 d122 d123 d124 d125 d 126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d 139 d140 d141 d142 d143 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 da 0 da1 da2 da3 da4 da5 x x 0 0 x 0 0 1 0 1 x: don?t care data format (2) (24 bits) code d120 d121 d122 d123 d124 d125 d 126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d 139 d140 d141 d142 d143 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 da 0 da1 da2 da3 da4 da5 x x 1 0 x 0 0 1 0 1 x: don?t care data format (3) (8 bits) code d136 d137 d138 d139 d140 d141 d142 d143 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 data format (4) (16 bits) code d128 d129 d130 d131 d132 d 133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 0 0 x 0 0 1 0 1 x:don?t care data format (5) (n bits) code dz dz+1 dz+2 dz+3 dz+4 dz+5 dz+6 dz+7 ????????????????????? d112 d113 d114 d115 d116 d117 d118 d119 ac0 1 ac1 1 ac2 1 ac3 1 ac4 1 ac5 1 ac6 1 ac7 1 ????????????????????? ac0 m-1 ac1 m-1 ac2 m-1 ac3 m-1 ac4 m-1 ac5 m-1 ac6 m-1 ac7 m-1 code d120 d121 d122 d123 d124 d125 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 ac0 m ac1 m ac2 m ac3 m ac4 m ac5 m ac6 m ac7 m da0 1 da1 1 da2 1 da3 1 da4 1 da5 1 x x 0 1 x 0 0 1 0 1 x: don?t care here, n = 8m + 16, z = 128 - 8m (m is an integer between 2 and 16 th at is the number of characters written as dcram data.) correspondence between the dcram address and the dcram data dcram address dcram data da0 1 to da5 1 ac0 1 to ac7 1 (da0 1 to da5 1 ) + 1 ac0 2 to ac7 2 (da0 1 to da5 1 ) + 2 ac0 3 to ac7 3 (da0 1 to da5 1 ) + (m ? 3) ac0 m-2 to ac7 m-2 (da0 1 to da5 1 ) + (m ? 2) ac0 m-1 to ac7 m-1 (da0 1 to da5 1 ) + (m ? 1) ac0 m to ac7 m
LC75810E/t no.7141-23/54 example 1: when n = 32 bits (m = 2: 2 characters dcram data write operation) code d112 d113 d114 d115 d116 d 117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 ac0 1 ac1 1 ac2 1 ac3 1 ac4 1 ac5 1 ac6 1 ac7 1 ac0 2 ac1 2 ac2 2 ac3 2 ac4 2 ac5 2 ac6 2 ac7 2 code d128 d129 d130 d131 d132 d 133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 da0 1 da1 1 da2 1 da3 1 da4 1 da5 1 x x 0 1 x 0 0 1 0 1 x: don?t care correspondence between the dcram address and the dcram data dcram address dcram data da0 1 to da5 1 ac0 1 to ac7 1 (da0 1 to da5 1 ) + 1 ac0 2 to ac7 2 example 2: when n = 80 bits (m = 8: 8 characters dcram data write operation) code d64 d65 d66 d67 d68 d69 d70 d71 d72 d73 d74 d75 d76 d77 d78 d79 ac0 1 ac1 1 ac2 1 ac3 1 ac4 1 ac5 1 ac6 1 ac7 1 ac0 2 ac1 2 ac2 2 ac3 2 ac4 2 ac5 2 ac6 2 ac7 2 code d80 d81 d82 d83 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 ac0 3 ac1 3 ac2 3 ac3 3 ac4 3 ac5 3 ac6 3 ac7 3 ac0 4 ac1 4 ac2 4 ac3 4 ac4 4 ac5 4 ac6 4 ac7 4 code d96 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 ac0 5 ac1 5 ac2 5 ac3 5 ac4 5 ac5 5 ac6 5 ac7 5 ac0 6 ac1 6 ac2 6 ac3 6 ac4 6 ac5 6 ac6 6 ac7 6 code d112 d113 d114 d115 d116 d 117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 ac0 7 ac1 7 ac2 7 ac3 7 ac4 7 ac5 7 ac6 7 ac7 7 ac0 8 ac1 8 ac2 8 ac3 8 ac4 8 ac5 8 ac6 8 ac7 8 code d128 d129 d130 d131 d132 d 133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 da0 1 da1 1 da2 1 da3 1 da4 1 da5 1 x x 0 1 x 0 0 1 0 1 x: don?t care correspondence between the dcram address and the dcram data dcram address dcram data da0 1 to da5 1 ac0 1 to ac7 1 (da0 1 to da5 1 ) + 1 ac0 2 to ac7 2 (da0 1 to da5 1 ) + 2 ac0 3 to ac7 3 (da0 1 to da5 1 ) + 3 ac0 4 to ac7 4 (da0 1 to da5 1 ) + 4 ac0 5 to ac7 5 (da0 1 to da5 1 ) + 5 ac0 6 to ac7 6 (da0 1 to da5 1 ) + 6 ac0 7 to ac7 7 (da0 1 to da5 1 ) + 7 ac0 8 to ac7 8
LC75810E/t no.7141-24/54 example 3: when n = 144 bits (m = 16: 16 characters dcram data write operation) code d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ac0 0 ac1 0 ac2 0 ac3 0 ac4 0 ac5 0 ac6 0 ac7 0 ac0 1 ac1 1 ac2 1 ac3 1 ac4 1 ac5 1 ac6 1 ac7 1 code d16 d17 d18 d19 d20 d21 d 22 d23 d24 d25 d26 d27 d28 d29 d30 d31 ac0 3 ac1 3 ac2 3 ac3 3 ac4 3 ac5 3 ac6 3 ac7 3 ac0 4 ac1 4 ac2 4 ac3 4 ac4 4 ac5 4 ac6 4 ac7 4 code d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 ac0 5 ac1 5 ac2 5 ac3 5 ac4 5 ac5 5 ac6 5 ac7 5 ac0 6 ac1 6 ac2 6 ac3 6 ac4 6 ac5 6 ac6 6 ac7 6 code d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ac0 7 ac1 7 ac2 7 ac3 7 ac4 7 ac5 7 ac6 7 ac7 7 ac0 8 ac1 8 ac2 8 ac3 8 ac4 8 ac5 8 ac6 8 ac7 8 code d64 d65 d66 d67 d68 d69 d70 d71 d72 d73 d74 d75 d76 d77 d78 d79 ac0 9 ac1 9 ac2 9 ac3 9 ac4 9 ac5 9 ac6 9 ac7 9 ac0 10 ac1 10 ac2 10 ac3 10 ac4 10 ac5 10 ac6 10 ac7 10 code d80 d81 d82 d83 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 ac0 11 ac1 11 ac2 11 ac3 11 ac4 11 ac5 11 ac6 11 ac7 11 ac0 12 ac1 12 ac2 12 ac3 12 ac4 12 ac5 12 ac6 12 ac7 12 code d96 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 ac0 13 ac1 13 ac2 13 ac3 13 ac4 13 ac5 13 ac6 13 ac7 13 ac0 14 ac1 14 ac2 14 ac3 14 ac4 14 ac5 14 ac6 14 ac7 14 code d112 d113 d114 d115 d116 d 117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 ac0 15 ac1 15 ac2 15 ac3 15 ac4 15 ac5 15 ac6 15 ac7 15 ac0 16 ac1 16 ac2 16 ac3 16 ac4 16 ac5 16 ac6 16 ac7 16 code d128 d129 d130 d131 d132 d 133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 da0 1 da1 1 da2 1 da3 1 da4 1 da5 1 x x 0 1 x 0 0 1 0 1 x: don?t care correspondence between the dcram address and the dcram data dcram address dcram data dcram address dcram data da0 1 to da5 1 ac0 1 to ac7 1 (da0 1 to da5 1 ) + 8 ac0 9 to ac7 9 (da0 1 to da5 1 ) + 1 ac0 2 to ac7 2 (da0 1 to da5 1 ) + 9 ac0 10 to ac7 10 (da0 1 to da5 1 ) + 2 ac0 3 to ac7 3 (da0 1 to da5 1 ) + 10 ac0 11 to ac7 11 (da0 1 to da5 1 ) + 3 ac0 4 to ac7 4 (da0 1 to da5 1 ) + 11 ac0 12 to ac7 12 (da0 1 to da5 1 ) + 4 ac0 5 to ac7 5 (da0 1 to da5 1 ) + 12 ac0 13 to ac7 13 (da0 1 to da5 1 ) + 5 ac0 6 to ac7 6 (da0 1 to da5 1 ) + 13 ac0 14 to ac7 14 (da0 1 to da5 1 ) + 6 ac0 7 to ac7 7 (da0 1 to da5 1 ) + 14 ac0 15 to ac7 15 (da0 1 to da5 1 ) + 7 ac0 8 to ac7 8 (da0 1 to da5 1 ) + 15 ac0 16 to ac7 16
LC75810E/t no.7141-25/54 ? alatch data write ? ? ? ? ? code d56 d57 d58 d59 d60 d61 d62 d63 d64 d65 d66 d67 d68 d69 d70 d71 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad 11 ad12 ad13 ad14 ad15 ad16 code d72 d73 d74 d75 d76 d77 d78 d79 d80 d81 d82 d 83 d84 d85 d86 d87 ad17 ad18 ad19 ad20 ad21 ad 22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 ad32 code d88 d89 d90 d91 d92 d93 d 94 d95 d96 d97 d98 d99 d100 d101 d102 d103 ad33 ad34 ad35 ad36 ad37 ad 38 ad39 ad40 ad41 ad42 ad43 ad44 ad45 ad46 ad47 ad48 code d104 d105 d106 d107 d108 d 109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 ad49 ad50 ad51 ad52 ad53 ad 54 ad55 ad56 ad57 ad58 ad59 ad60 ad61 ad62 ad63 ad64 code d120 d121 d122 d123 d124 d 125 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 ad65 ad66 ad67 ad68 ad69 ad 70 ad71 ad72 ad73 ad74 ad75 ad76 ad77 ad78 ad79 ad80 code d136 d137 d138 d139 d140 d141 d142 d143 x x x 0 0 1 1 0 x: don?t care ad1 to ad80: adata display data in addition to the 5 7, 5 8, 5 9, 6 7, 6 8, or 6 9 dot matrix display data (mdata), the LC75810E/t also supports an accessory display of 5 or 6 segments ( adata) at each display digit, and allows ar bitrary data to be displayed directly without going through cgrom or cgram. the figure below shows the correspondence between that data and the display. when adn = 1 (where n is an integer between 1 and 80), the se gment corresponding to that data will be turned on. 5-dot font width (5 7, 5 8, or 5 9 dots) com1 com2 com3 com4 com5 com6 com7 com8 s80/com9 s79/com10 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 ad76 ad77 ad78 ad79 ad80 ad2 ad1 ad3 ad4 ad5 ad7 ad8 ad9 ad10 ad6 ad72 ad71 ad73 ad74 ad75 s71 s72 s73 s74 s75 s76 s77 s78 com10/s79 com9/s80
LC75810E/t no.7141-26/54 6-dot font width (6 7, 6 8, or 6 9 dots) com1 com2 com3 com4 com5 com6 com7 com8 s80/com9 s79/com10 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 ad73 ad74 ad75 ad76 ad77 ad2 ad1 ad3 ad4 ad5 ad8 ad9 ad10 ad11 ad7 ad68 ad67 ad69 ad70 ad71 s67 s68 s69 s70 s71 s72 s73 s74 s75 s76 s77 s78 ad6 ad12 ad72 ad78 correspondence between adata and the output pins adata corresponding output pin adata correspondi ng output pin adata co rresponding output pin ad1 s1 ad31 s31 ad61 s61 ad2 s2 ad32 s32 ad62 s62 ad3 s3 ad33 s33 ad63 s63 ad4 s4 ad34 s34 ad64 s64 ad5 s5 ad35 s35 ad65 s65 ad6 s6 ad36 s36 ad66 s66 ad7 s7 ad37 s37 ad67 s67 ad8 s8 ad38 s38 ad68 s68 ad9 s9 ad39 s39 ad69 s69 ad10 s10 ad40 s40 ad70 s70 ad11 s11 ad41 s41 ad71 s71 ad12 s12 ad42 s42 ad72 s72 ad13 s13 ad43 s43 ad73 s73 ad14 s14 ad44 s44 ad74 s74 ad15 s15 ad45 s45 ad75 s75 ad16 s16 ad46 s46 ad76 s76 ad17 s17 ad47 s47 ad77 s77 ad18 s18 ad48 s48 ad78 s78 ad19 s19 ad49 s49 ad79 s79 ad20 s20 ad50 s50 ad80 s80 ad21 s21 ad51 s51 ad22 s22 ad52 s52 ad23 s23 ad53 s53 ad24 s24 ad54 s54 ad25 s25 ad55 s55 ad26 s26 ad56 s56 ad27 s27 ad57 s57 ad28 s28 ad58 s58 ad29 s29 ad59 s59 ad30 s30 ad60 s60
LC75810E/t no.7141-27/54 ? cgram data write ? ? ? ? ? code d80 d81 d82 d83 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 cd1 cd2 cd3 cd4 cd5 cd6 cd7 cd8 cd9 cd10 cd11 cd12 cd13 cd14 cd15 cd16 code d96 d97 d98 d99 d100 d101 d 102 d103 d104 d105 d106 d 107 d108 d109 d110 d111 cd17 cd18 cd19 cd20 cd21 cd22 cd23 cd24 cd25 cd26 cd27 cd28 cd29 cd30 cd31 cd32 code d112 d113 d114 d115 d116 d 117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 cd33 cd34 cd35 cd36 cd37 cd38 cd39 cd40 cd41 cd42 cd43 cd44 cd45 x x x code d128 d129 d130 d131 d132 d 133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 wm x x 0 0 1 1 1 x:don?t care ca0 to ca7: cgram address ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 lsb msb least significant bit most significant bit cd1 to cd45: cgram data (5 7, 5 8, or 5 9 dot matrix display data) the bit cdn (where n is an integer between 1 and 45) corresponds to the 5 7, 5 8, or 5 9 dot matrix display data. the figure below shows that correspondence. when cdn is 1, the dots which correspond to that data will be turned on. cd1 cd2 cd3 cd4 cd5 cd6 cd7 cd8 cd9 cd10 cd11 cd12 cd13 cd14 cd15 cd16 cd17 cd18 cd19 cd20 cd21 cd22 cd23 cd24 cd25 cd26 cd27 cd28 cd29 cd30 cd31 cd32 cd33 cd34 cd35 cd36 cd37 cd38 cd39 cd40 cd41 cd42 cd43 cd44 cd45 *22: cd1 to cd35: 5 7 dot matrix display data cd1 to cd40: 5 8 dot matrix display data cd1 to cd45: 5 9 dot matrix display data
LC75810E/t no.7141-28/54 wm: sets the method of writing data to cgram. wm cgram data write method 0 normal cgram data write (specifies a cgram address and write a cgram data.) 1 double write mode cgram data write (s pecifies two cgram addresses and writes two cgram data to those addresses.) ? 23: ? cgram data write method when wm is 0. cgram data write finishes cgram data write finishes cgram data write finishes cgram data write finishes instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) instruction execution time (27 s) (6) (6) (6) 64 bits 64 bits 64 bits 64 bits (6) ce di cgram ccb address ccb address ccb address ccb address ? cgram data write method when wm is 1. cgram data write finishes cgram data write finishes cgram data write finishes instruction execution time (40.5 s) instruction execution time (40.5 s) instruction execution time (40.5 s) (7) (7) 120 bits 120 bits (7) ce di cgram 120 bits ccb address ccb address ccb address note that the instruction execution times of 27 s and 40.5 s apply when fosc = 300 khz, and that these times will differ when the oscillator frequency fosc differs. data format (6) (64 bits) code d80 d81 d82 d83 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 cd1 cd2 cd3 cd4 cd5 cd6 cd7 cd8 cd9 cd10 cd11 cd12 cd13 cd14 cd15 cd16 code d96 d97 d98 d99 d100 d101 d 102 d103 d104 d105 d106 d107 d108 d109 d110 d111 cd17 cd18 cd19 cd20 cd21 cd22 cd23 cd24 cd25 cd26 cd27 cd28 cd29 cd30 cd31 cd32 code d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 cd33 cd34 cd35 cd36 cd37 cd38 cd39 cd40 cd41 cd42 cd43 cd44 cd45 x x x code d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 0 x x 0 0 1 1 1 x: don?t care
LC75810E/t no.7141-29/54 data format (7) (120 bits) code d24 d25 d26 d27 d28 d29 d30 d31 d32 d33 d34 d35 d36 d37 d38 d39 cd1 1 cd2 1 cd3 1 cd4 1 cd5 1 cd6 1 cd7 1 cd8 1 cd9 1 cd10 1 cd11 1 cd12 1 cd13 1 cd14 1 cd15 1 cd16 1 code d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 cd17 1 cd18 1 cd19 1 cd20 1 cd21 1 cd22 1 cd23 1 cd24 1 cd25 1 cd26 1 cd27 1 cd28 1 cd29 1 cd30 1 cd31 1 cd32 1 code d56 d57 d58 d59 d60 d61 d62 d63 d64 d65 d66 d67 d68 d69 d70 d71 cd33 1 cd34 1 cd35 1 cd36 1 cd37 1 cd38 1 cd39 1 cd40 1 cd41 1 cd42 1 cd43 1 cd44 1 cd45 1 x x x code d72 d73 d74 d75 d76 d77 d78 d79 d8 0 d81 d82 d83 d84 d85 d86 d87 ca0 1 ca1 1 ca2 1 ca3 1 ca4 1 ca5 1 ca6 1 ca7 1 cd1 2 cd2 2 cd3 2 cd4 2 cd5 2 cd6 2 cd7 2 cd8 2 code d88 d89 d90 d91 d92 d93 d 94 d95 d96 d97 d98 d99 d100 d101 d102 d103 cd9 2 cd10 2 cd11 2 cd12 2 cd13 2 cd14 2 cd15 2 cd16 2 cd17 2 cd18 2 cd19 2 cd20 2 cd21 2 cd22 2 cd23 2 cd24 2 code d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 cd25 2 cd26 2 cd27 2 cd28 2 cd29 2 cd30 2 cd31 2 cd32 2 cd33 2 cd34 2 cd35 2 cd36 2 cd37 2 cd38 2 cd39 2 cd40 2 code d120 d121 d122 d123 d124 d125 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 cd41 2 cd42 2 cd43 2 cd44 2 cd45 2 x x x ca0 2 ca1 2 ca2 2 ca3 2 ca4 2 ca5 2 ca6 2 ca7 2 code d136 d137 d138 d139 d140 d141 d142 d143 1 x x 0 0 1 1 1 x: don?t care correspondence between the cgram address and the cgram data cgram address cgram data ca0 1 to ca7 1 cd1 1 to cd45 1 ca0 2 to ca7 2 cd1 2 to cd45 2
LC75810E/t no.7141-30/54 ? set display contrast ? ? ? ? ? code d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 ct0 ct1 ct2 ct3 x x x x ctc x x 0 1 0 0 0 x:don?t care ct0 to ct3: sets the display contrast (11 steps) ct0 ct1 ct2 ct3 lcd drive 4/4 bias voltage supply v lcd 0 level 0 0 0 0 0.94v lcd = v lcd -(0.03v lcd 2) 1 0 0 0 0.91v lcd = v lcd -(0.03v lcd 3) 0 1 0 0 0.88v lcd = v lcd -(0.03v lcd 4) 1 1 0 0 0.85v lcd = v lcd -(0.03v lcd 5) 0 0 1 0 0.82v lcd = v lcd -(0.03v lcd 6) 1 0 1 0 0.79v lcd = v lcd -(0.03v lcd 7) 0 1 1 0 0.76v lcd = v lcd -(0.03v lcd 8) 1 1 1 0 0.73v lcd = v lcd -(0.03v lcd 9) 0 0 0 1 0.70v lcd = v lcd -(0.03v lcd 10) 1 0 0 1 0.67v lcd = v lcd -(0.03v lcd 11) 0 1 0 1 0.64v lcd = v lcd -(0.03v lcd 12) ctc: sets the display contra st adjustment circuit state ctc display contrast adj ustment circuit state 0 the display contrast adjustment circuit is disabled, and the v lcd 0 pin level is forced to the v lcd level. 1 the display contrast adjustment circuit oper ates, and the display c ontrast is adjusted. note that although the display contrast can be adjusted by operating the built-in disp lay contrast adjustment circuit, it is also possible to be adjusted by varying the voltage level on the lcd driver block power supply v lcd pin. however, the level on v lcd 0 must be greater than or equal to 4.5v.
LC75810E/t no.7141-31/54 notes on the power on and power off sequences the following sequences must be observed when power is turned on and off. (see figure 3.) ? at power on: logic block power supply (v dd ) on lcd driver block power supply (v lcd ) on. ? at power off: lcd driver block power supply (v lcd ) off logic block power supply (v dd ) off. however, if the logic and lcd driver block use a shared power supply, then the power supplies can be turned on and off at the same time. t2 twres v il v ih t3 t1 instruction execution res v dd v lcd initial state settings display off display on ?display on/off control? instruction execution (turning the display off) ?display on/off control? instruction execution (turning the display on) initial state setting ? set display technique ? dcram data write ? alatch data write (if alatch is used) ? cgram data write (if cgram is used) ? set ac and sc addresses ? set display contrast (if the display contrast adjustment circuit is used) ? t1 0 ? t2 > 0 ? t3 0 (t2 > t3) ? twres ? ? ? 1 s min display off display state figure 3 ??????
LC75810E/t no.7141-32/54 1/8 duty, 1/4 bias drive technique v lcd 3 v ss v ss v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 3 v lcd 2 v lcd 2 v lcd 1 v lcd 1 v lcd 0 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 lcd driver output when all lcd segments corresponding to com1 to com8 are turned on lcd driver output when all lcd segments corresponding to com1 to com8 are turned off com8 com2 com1 lcd driver output when only lcd segments corresponding to com2 are turned on lcd driver output when only lcd segments corresponding to com1 are turned on t8 t8 8 1 f8 t8 = when a ?set display technique? instruction with fc = 0 is executed: f8 = when a ?set display technique? instruction with fc = 1 is executed: f8 = fosc 3072 fosc 1536
LC75810E/t no.7141-33/54 1/9 duty, 1/4 bias drive technique v lcd 3 v ss v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 lcd driver output when all lcd segments corresponding to com1 to com9 are turned on lcd driver output when all lcd segments corresponding to com1 to com9 are turned off com9 com2 com1 lcd driver output when only lcd segments corresponding to com2 are turned on lcd driver output when only lcd segments corresponding to com1 are turned on t9 t9 9 1 f9 t9 = when a ?set display technique? instruction with fc = 0 is executed: f9 = when a ?set display technique? instruction with fc = 1 is executed: f9 = fosc 3456 fosc 1728
LC75810E/t no.7141-34/54 1/10 duty, 1/4 bias drive technique v lcd 3 v ss v ss v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 3 v lcd 2 v lcd 2 v lcd 1 v lcd 1 v lcd 0 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v lcd 3 v lcd 2 v lcd 1 v lcd 0 lcd driver output when all lcd segments corresponding to com1 to com10 are turned on lcd driver output when all lcd segments corresponding to com1 to com10 are turned off com10 com2 com1 lcd driver output when only lcd segments corresponding to com2 are turned on lcd driver output when only lcd segments corresponding to com1 are turned on t10 10 1 f10 t10 = when a ?set display technique? instruction with fc = 0 is executed: f10 = when a ?set display technique? instruction with fc = 1 is executed: f10 = fosc 3840 fosc 1920 t10
LC75810E/t no.7141-35/54 sample application circuit 1 5 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with normal panels) c 0.047 f + 8 v + 5 v from the controller com9/s80 com10/s79 s78 s77 s76 s10 s9 s8 s7 s6 s5 s4 s3 s2 lcd panel s1 com8 com7 com6 com5 com4 com3 com2 com1 ccc res ce cl di osc v lcd 2 v lcd 1 v lcd 0 v lcd v ss v dd v lcd 3 open sample application circuit 2 5 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with large panels) from the controller com9/s80 com10/s79 s78 s77 s76 s10 s9 s8 s7 s6 s5 s4 s3 s2 lcd panel s1 com8 com7 com6 com5 com4 com3 com2 com1 cc r r r r c +8 v + 5 v c 0.047 f 10 k ? r 2.2 k ? res ce cl di osc v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v dd v lcd
LC75810E/t no.7141-36/54 sample application circuit 3 5 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with normal panels) from the controller com10/s79 s78 s77 s76 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 com8 com7 com6 com5 com4 com3 com2 com1 ccc c 0.047 f + 8 v + 5 v res ce cl di osc v lcd 2 v lcd 1 v lcd 0 v lcd v ss v dd v lcd 3 open lcd panel s80/com9 sample application circuit 4 5 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with large panels) from the controller com10/s79 s78 s77 s76 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 com8 com7 com6 com5 com4 com3 com2 com1 cc r r r r c +8 v + 5 v res ce cl di osc v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v dd c 0.047 f 10 k ? r 2.2 k ? v lcd lcd panel s80/com9
LC75810E/t no.7141-37/54 sample application circuit 5 5 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with normal panels) from the controller s78 s77 s76 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 com8 com7 com6 com5 com4 com3 com2 com1 ccc c 0.047 f + 8 v + 5 v res ce cl di osc v lcd 2 v lcd 1 v lcd 0 v lcd v ss v dd v lcd 3 open lcd panel s80/com9 s79/com10 sample application circuit 6 5 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with large panels) from the controller s79/com10 s78 s77 s76 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 com8 com7 com6 com5 com4 com3 com2 com1 cc r r r r c +8 v + 5 v c 0.047 f 10 k ? r 2.2 k ? res ce cl di osc v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v dd v lcd lcd panel s80/com9
LC75810E/t no.7141-38/54 sample application circuit 7 6 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with normal panels) from the controller com9/s80 com10/s79 s75 s74 s73 s10 s9 s8 s7 s6 s5 s4 s3 s2 lcd panel s1 com8 com7 com6 com5 com4 com3 com2 com1 ccc c 0.047 f + 8 v + 5 v res ce cl di osc v lcd 2 v lcd 1 v lcd 0 v lcd v ss v dd v lcd 3 open s11 s12 s76 s77 s78 open sample application circuit 8 6 7 dot matrix, 1/8 duty, 1/4 bias drive (for use with large panels) s78 s76 from the controller com9/s80 com10/s79 s75 s74 s73 s10 s9 s8 s7 s6 s5 s4 s3 s2 lcd panel s1 com8 com7 com6 com5 com4 com3 com2 com1 cc r r r r c + 8 v + 5 v c 0.047 f 10 k ? r 2.2 k ? res ce cl di osc v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v dd v lcd open s11 s12 s77
LC75810E/t no.7141-39/54 sample application circuit 9 6 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with normal panels) from the controller com10/s79 s78 s77 s73 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 com8 com7 com6 com5 com4 com3 com2 com1 ccc c 0.047 f + 8 v + 5 v res ce cl di osc v lcd 2 v lcd 1 v lcd 0 v lcd v ss v dd v lcd 3 open lcd panel s80/com9 s11 s12 s74 s75 s76 open sample application circuit 10 6 8 dot matrix, 1/9 duty, 1/4 bias drive (for use with large panels) from the controller com10/s79 s78 s77 s76 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 com8 com7 com6 com5 com4 com3 com2 com1 cc r r r r c +8 v +5 v c 0.047 f 10 k ? r 2.2 k ? res ce cl di osc v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v dd v lcd lcd panel s80/com9 s11 s12 s75 s74 s73 open
LC75810E/t no.7141-40/54 sample application circuit 11 6 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with normal panels) from the controller s78 s77 s76 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 com8 com7 com6 com5 com4 com3 com2 com1 ccc c 0.047 f + 8 v + 5 v res ce cl di osc v lcd 2 v lcd 1 v lcd 0 v lcd v ss v dd v lcd 3 open lcd panel s80/com9 s79/com10 s11 s12 s75 s74 s73 sample application circuit 12 6 9 dot matrix, 1/10 duty, 1/4 bias drive (for use with large panels) s76 from the controller s79/com10 s75 s74 s73 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 com8 com7 com6 com5 com4 com3 com2 com1 cc r r r r c + 8 v + 5 v c 0.047 f 10 k ? r 2.2 k ? res ce cl di osc v lcd 3 v lcd 2 v lcd 1 v lcd 0 v ss v dd v lcd lcd panel s80/com9 s78 s77 s11 s12
LC75810E/t no.7141-41/54 operation initializes the ic. the display is in the off state. sets to the 1/8 duty 1/4 bias display technique, the 32 digits 2 lines display structure, and the 5-dot font width at each digit. writes the display data ?s? to dcram address 00h. writes the display data ?a? to dcram address 01h. writes the display data ?n? to dcram address 02h. writes the display data ?y? to dcram address 03h. writes the display data ?o? to dcram address 04h. writes the display data ? ? to dcram address 05h. writes the display data ?i? to dcram address 06h. writes the display data ?c? to dcram address 07h. writes the display data ? ? to dcram address 08h. writes the display data ?l? to dcram address 09h. writes the display data ?c? to dcram address 0ah. writes the display data ?7? to dcram address 0bh. writes the display data ?5? to dcram address 0ch. writes the display data ?8? to dcram address 0dh. writes the display data ?1? to dcram address 0eh. display d140 to d143 8 a 4 4 5 4 2 4 4 2 4 4 3 3 3 3 d136 to d13 9 0 1 1 e 9 f 0 9 3 0 c 3 7 5 8 1 d132 to d135 0 0 d128 to d131 1 0 d124 to d127 5 d120 to d12 3 3 d116 to d119 instruction (hexadecimal) d112 to d11 5 power application (initialization with the res pin) set display technique dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 continued on next page. lsb msb sample 1 showing the correspondence between instructions and the display (using the lc75810-8725 with a 5 7 dots, 16 digits 1 line display)
LC75810E/t no.7141-42/54 operation writes the display data ?0? to dcram address 0fh. writes the display data ? ? to dcram address 10h. writes the display data ?l? to dcram address 11h. writes the display data ?c? to dcram address 12h. writes the display data ?d? to dcram address 13h. writes the display data ? ? to dcram address 14h. writes the display data ?d? to dcram address 15h. writes the display data ?r? to dcram address 16h. writes the display data ?i? to dcram address 17h. writes the display data ?v? to dcram address 18h. writes the display data ?e? to dcram address 19h. writes the display data ?r? to dcram address 1ah. writes the display data ? ? to dcram address 1bh. writes the display data ? ? to dcram address 1ch. writes the display data ? ? to dcram address 1dh. writes the display data ? ? to dcram address 1eh. writes the display data ? ? to dcram address 1fh. display d140 to d143 3 2 4 4 4 2 4 5 4 5 4 5 2 2 2 2 2 d136 to d139 0 0 c 3 4 0 4 2 9 6 5 2 0 0 0 0 0 d132 to d135 d128 to d131 d124 to d127 d120 to d123 d116 to d119 instruction (hexadecunal) d112 to d115 dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) no. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 msb lsb continued from perceding page. continued on next page.
LC75810E/t no.7141-43/54 operation writes the display data ?d? to dcram address 20h. writes the display data ?o? to dcram address 21h. writes the display data ?t? to dcram address 22h. writes the display data ? ? to dcram address 23h. writes the display data ?m? to dcram address 24h. writes the display data ?a? to dcram address 25h. writes the display data ?t? to dcram address 26h. writes the display data ?r? to dcram address 27h. writes the display data ?i? to dcram address 28h. writes the display data ?x? to dcram address 29h. writes the display data ? ? to dcram address 2ah. writes the display data ?t? to dcram address 2bh. writes the display data ?y? to dcram address 2ch. writes the display data ?p? to dcram address 2dh. writes the display data ?e? to dcram address 2eh. writes the display data ? ? to dcram address 2fh. sets ac to the dcram address 00h, sc to the horizontal dot address 0h and the vertical dot address 0h. display d140 to d143 4 4 5 2 4 4 5 5 4 5 2 5 5 5 4 a 2 d136 to d139 4 f 4 0 d 1 4 2 9 8 0 4 9 0 5 0 0 d132 to d13 5 2 0 d128 to d131 0 0 d124 to d127 0 d120 to d123 0 d116 to d119 0 instruction (hexadecimal) d112 to d115 dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) set ac and sc addresses 0 no. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 msb lsb continued from preceding page. continued on next page.
LC75810E/t no.7141-44/54 operation turns on the lcd for all digits (16 digits) in mdata. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. display d140 to d143 4 c c c c c c c c c c c c c c c c d136 to d139 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d132 to d135 f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d128 to d131 f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d124 to d12 7 f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d120 to d12 3 f 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 d116 to d11 9 instruction (hexadecimal) d112 to d11 5 display on/off control display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll no. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 msb lsb continued from preceding page continued on next page.
LC75810E/t no.7141-45/54 operation shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. sets ac to the dcram address 00h, sc to the horizontal dot address 0h and the vertical dot address 0h. shifts just the mdata display two dots to the up. shifts just the mdata display two dots to the up. shifts just the mdata display two dots to the up. shifts just the mdata display two dots to the up. sets to power saving mode, turns off the lcd for all digits. turns on the lcd for all digits (16 digits) in mdata. sets ac to the dcram address 00h, sc to the horizontal dot address 0h and the vertical dot address 0h. display d140 to d143 c c c c c c 2 c c c c 4 4 2 d136 to d13 9 0 0 0 0 0 0 0 0 0 0 0 8 1 0 d132 to d13 5 0 0 0 0 0 0 0 0 0 0 0 0 f 0 d128 to d131 0 0 0 0 0 0 0 2 2 2 2 0 f 0 d124 to d12 7 0 0 0 0 0 0 0 0 0 0 0 0 f 0 d120 to d123 3 3 3 3 3 3 0 0 0 0 0 0 f 0 d116 to d11 9 0 0 instruction (hexadecimal) d112 to d115 display scroll display scroll display scroll display scroll display scroll display scroll set ac and sc addresses 0 display scroll display scroll display scroll display scroll display on/off control display on/off control set ac and sc addresses 0 no. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 msb lsb continued from preceding page.
LC75810E/t no.7141-46/54 d84 to d87 4 5 2 d80 to d83 3 2 0 d76 to d79 4 4 5 d72 to d75 c 5 8 d68 to d71 2 5 4 d64 to d67 0 6 9 d60 to d63 4 4 5 d56 to d59 3 9 2 display writes the display data "s" "a" "n" "y" "o" " " "i" "c" " " "l" "c" "7" "5" "8" "1" "0" to dcram addresses 00h to 0fh. writes the display data " " "l" "c" "d" " " "d" "r" "i" "v" "e" "r" " " " " " " " " " " to dcram addresses 10h to 1fh. writes the display data "d" "o" "t" " " "m" "a" "t" "r" "i" "x" " " "t" "y" "p" "e" " " to dcram addresses 20h to 2fh. d52 to d55 4 5 5 d140 t o d143 a a a d48 to d51 9 2 4 d136 t o d139 2 2 2 d44 to d47 2 4 4 d132 to d135 0 1 2 d40 to d43 0 4 1 d128 t o d131 0 0 0 d36 to d39 4 2 4 d124 t o d127 3 2 2 d32 to d35 f 0 d d120 t o d123 0 0 0 d28 to d31 5 4 2 d116 t o d119 3 2 4 d24 to d27 9 4 0 d112 t o d115 1 0 5 d20 to d23 4 4 5 d108 t o d111 3 2 5 d16 to d19 e 3 4 d104 t o d107 8 0 0 d12 to d15 4 4 4 d100 t o d103 3 2 5 d8 to d11 1 c f d96 to d99 5 0 9 d4 to d7 5 2 4 d92 to d95 3 2 5 instruction d0 to d3 dcram data write (super-increment mode) 3 dcram data write (super-increment mode) 0 dcram data write (super-increment mode) 4 instruction d88 to d91 dcram data write (super-increment mode) 7 dcram data write (super-increment mode) 0 dcram data write (super-increment mode) 4 no. 3 to 18 19 to 34 35 to 50 no. 3 to 18 19 to 34 35 to 50 lsb msb msb lsb notes ? 24: in sample 1 showing the correspondence between instructions and the display, a 16 digits 1 line 5 7 dot matrix lcd is used, and cgram and alatch are not used. ? 25: the data format will have the following format if super-increment mode is used for the ?dcram data write? instructions (num bers 3 to 50) in sample 1 showing the correspondence between instructions and the display. note that the sample below shows 48 characters of dcram data being divided into 3 separate ?dcram data write? instruction exec utions in the super-increment mode.
LC75810E/t no.7141-47/54 operation initializes the ic. the display is in the off state. sets to the 1/8 duty 1/4 bias display technique, the 32 digits 2 lines display structure, and the 6-dot font width at each digit. writes the display data "s" to dcram address 00h. writes the display data "a" to dcram address 01h. writes the display data "n" to dcram address 02h. writes the display data "y" to dcram address 03h. writes the display data "o" to dcram address 04h. writes the display data " " to dcram address 05h. writes the display data "l" to dcram address 06h. writes the display data "c" to dcram address 07h. writes the display data "7" to dcram address 08h. writes the display data "5" to dcram address 09h. writes the display data "8" to dcram address 0ah. writes the display data "1" to dcram address 0bh. writes the display data "0" to dcram address 0ch. writes the display data " " to dcram address 0dh. writes the display data "l" to dcram address 0eh. display d140 to d143 8 a 4 4 5 4 2 4 4 3 3 3 3 3 2 4 d136 to d139 0 1 1 e 9 f 0 c 3 7 5 8 1 0 0 c d132 to d13 5 0 0 d128 to d131 5 0 d124 to d127 5 d120 to d123 3 d116 to d119 instruction (hexadecimal) d112 to d115 power application (initialization with the res pin) set display technique dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) no 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 msb sample 2 showin g the correspondence between instructions and the displa y ( usin g the lc75810-8725 with a 6 7 dots, 13 di g its 1 line displa y) continued on next page. lsb
LC75810E/t no.7141-48/54 operation writes the display data "c" to dcram address 0fh. writes the display data "d" to dcram address 10h. writes the display data " " to dcram address 11h. writes the display data "d" to dcram address 12h. writes the display data "r" to dcram address 13h. writes the display data "i" to dcram address 14h. writes the display data "v" to dcram address 15h. writes the display data "e" to dcram address 16h. writes the display data "r" to dcram address 17h. writes the display data " " to dcram address 18h. writes the display data " " to dcram address 19h. writes the display data "d" to dcram address 20h. writes the display data "o" to dcram address 21h. writes the display data "t" to dcram address 22h. writes the display data " " to dcram address 23h. writes the display data "m" to dcram address 24h. writes the display data "a" to dcram address 25h. display d140 to d14 3 4 4 2 4 5 4 5 4 5 2 a a 4 5 2 4 4 d136 to d139 3 4 0 4 2 9 6 5 2 0 0 1 f 4 0 d 1 d132 to d13 5 2 2 d128 to d131 0 0 d124 to d127 4 d120 to d123 4 d116 to d119 instruction (hexadecimal) d112 to d115 dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) no. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 msb lsb continued from preceding page. continued on next page.
LC75810E/t no.7141-49/54 operation writes the display data "t" to dcram address 26h. writes the display data "r" to dcram address 27h. writes the display data "i" to dcram address 28h. writes the display data "x" to dcram address 29h. writes the display data " " to dcram address 2ah. writes the display data " " to dcram address 2bh. writes the display data " " to dcram address 2ch. sets ac to the dcram address 00h, sc to the horizontal dot address 0h and the vertical dot address 0h. turns on the lcd for all digits (13 digits) in mdata . shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. display d140 to d143 5 5 4 5 2 2 a 2 4 c c c c c c c c d136 to d139 4 2 9 8 0 0 0 0 1 0 0 0 0 0 0 0 0 d132 to d13 5 2 0 1 0 0 0 0 0 0 0 0 d128 to d131 0 0 f 0 0 0 0 0 0 0 0 d124 to d127 0 f 0 0 0 0 0 0 0 0 d120 to d123 0 f 3 3 3 3 3 3 3 3 d116 to d119 0 instruction (hexadecimal) d112 to d11 5 dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) dcram data write (normal increment mode) set ac and sc addresses 0 display on/off control display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll no. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 msb lsb continued from preceding page. continued on next page.
LC75810E/t no.7141-50/54 operation shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. shifts just the mdata display three dots to the left. sets ac to the dcram address 00h, sc to the horizontal dot address 0h and the vertical dot address 0h. shifts just the mdata display two dots to the up. shifts just the mdata display two dots to the up. display d140 to d143 c c c c c c c c c c c c c c 2 c c d136 to d139 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d132 to d135 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d128 to d131 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 d124 to d127 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d120 to d123 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 0 0 d116 to d119 0 instruction (hexadecimal) d112 to d115 display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll display scroll set ac and sc addresses 0 display scroll display scroll no. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 msb lsb continued from preceding page. continued on next page.
LC75810E/t no.7141-51/54 operation shifts just the mdata display two dots to the up. shifts just the mdata display two dots to the up. sets to power saving mode, turns off the lcd for all digits. turns on the lcd for all digits (13 digits) in mdata. sets ac to the dcram address 00h, sc to the horizontal dot address 0h and the vertical dot address 0h. display d140 to d143 c c 4 4 2 d136 to d139 0 0 8 1 0 d132 to d13 5 0 0 0 1 0 d128 to d131 2 2 0 f 0 d124 to d12 7 0 0 0 f 0 d120 to d12 3 0 0 0 f 0 d116 to d11 9 0 instruction (hexadecimal) d112 to d11 5 display scroll display scroll display on/off control display on/off control set ac and sc addresses 0 no. 69 70 71 72 73 msb lsb continued from preceding page.
LC75810E/t no.7141-52/54 d108 to d111 3 5 2 d104 to d107 8 2 0 d100 to d103 3 4 5 d96 to d99 5 5 8 d92 to d95 3 5 4 d88 to d91 7 6 9 d84 to d87 4 4 5 d80 to d83 3 9 2 d76 to d79 4 5 5 d72 to d75 c 2 4 d68 to d71 2 4 4 d64 to d67 0 4 1 d60 to d63 4 2 4 d56 to d59 f 0 d operation writes the display data "s" "a" "n" "y" "o" " " "l" "c" "7" "5" "8" "1" "0" to dcram addresses 00h to 0ch. writes the display data " " "l" "c" "d" " " "d" "r" "i" "v" "e" "r" " " " " to dcram addresses 0dh to 19h. writes the display data "d" "o" "t" " " "m" "a" "t" "r" "i" "x" " " " " " " to dcram addresses 20h to 2ch. d52 to d55 5 4 2 d140 to d14 3 a a a d48 to d51 9 4 0 d136 to d13 9 2 2 2 d44 to d47 4 4 5 d132 to d13 5 0 0 2 d40 to d43 e 3 4 d128 to d131 0 d 0 d36 to d39 4 4 4 d124 to d127 3 2 2 d32 to d35 1 c f d120 to d12 3 0 0 0 d28 to d31 5 2 4 d116 to d119 3 2 2 instruction d24 to d27 dcram data write (super-increment mode) 3 dcram data write (super-increment mode) 0 dcram data write (super-increment mode) 4 instruction d112 to d11 5 dcram data write (super-increment mode) 1 dcram data write (super-increment mode) 0 dcram data write (super-increment mode) 0 no. 3 to 15 16 to 28 29 to 41 no. 3 to 15 16 to 28 29 to 41 notes ? 26: in sample 2 showing the correspondence between instructions and the display, a 13 digits 1 line 6 7 dot matrix lcd is used, and cgram and alatch are not used. ? 27: the data format will have the following format if super-increment mode is used for the ?dcram data write? instructions (num bers 3 to 41) in sample 2 showing the correspondence between instructions and the display. note that the sample below shows 39 characters of dcram data being divided into 3 separate ?dcram data write? instruction exec utions in the super-increment mode. msb msb lsb lsb
LC75810E/t no.7141-53/54
LC75810E/t no.7141-54/54 specifications of any and all sanyo semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides informati on as of march, 2002. specifications and information herein are subject to change without notice.

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